1. Field of the Invention
The present invention relates to an organic thin film transistor and a flat panel display device including the same, and more particularly, to an organic thin film transistor capable of precisely transmitting signals, the operation thereof and a flat panel display device including the same.
2. Description of the Related Art
Flat panel display devices, such as liquid crystal display devices, organic electroluminescent display devices, inorganic electroluminescent display devices, and the like, include thin film transistors (TFTs). A TFT is used as a switching device controlling the operation of a pixel or as a driving device for driving a pixel.
The TFT includes a semiconductor layer having source and drain regions doped with a high-concentration impurity and a channel region formed between the source region and the drain region, a gate electrode insulated from the semiconductor layer and disposed above the channel region, and source and drain electrodes respectively contacting the source and drain regions.
Flat display devices have become thin and flexible. In order to obtain a flexible flat display device, a plastic substrate is used instead of a glass substrate. However, the use of a plastic substrate requires a low temperature process. Therefore, a conventional transistor composed of polysilicon cannot be used.
In order to solve this problem, organic semiconductors have been developed. Organic semiconductors can be processed at low temperatures such that TFTs can be manufactured at low costs.
FIG. 1 is a sectional view of a conventional organic TFT. Referring to FIG. 1, source and drain electrodes 11, an organic semiconductor layer 12, and a gate electrode 14 are formed on a surface of a substrate 10. The source and drain electrodes 11 are insulated from the gate electrode 14 by a gate insulator 13. The insulator 13 has a thickness within a predetermined range. When the thickness of the gate insulator 13 is too great, an interaction between the channel region of the organic semiconductor layer 12 and the gate electrode is not consistent across the entire channel region, thus decreasing operating performance. On the other hand, when the thickness of the gate insulator 13 is too small, parasitic capacitance may be increased between the gate electrode 14 and both the source and drain electrodes 11 in regions indicated by “Ac”. The capacitance between the gate electrode 14 and both the source and drain electrodes 11 is given by
  C  =      k    ⁢                  A        r            d      where k is the dielectric constant of the insulator 13, Ar is the area where the source and drain electrodes 11 and the gate electrode 14 overlap, and d is the distance between the source and drain electrodes 11 and the gate electrode 14. For example, as the thickness the gate insulator 13 decreases, C increases, resulting in a parasitic capacitance between the source and drain electrodes 11 and the gate electrode 14, which is undesired. The parasitic capacitance causes a signal delay such that the operating speed of a device becomes lower. Since flat display devices must display gradation with accuracy and quick response, such a signal delay must be overcome.